Media IC & System Lab
Chih-Hsueh "Josh" Huang
githubhjs
Digital IC Design engineer with 20 yrs of experience, including design, verification, scripting, automation, LEC, LINT, SYN. Open to work in Japan/Singapore.
huangjs@gmail.com Taiwan
Hua-Chen (Matilda) Wu
trista-csee
Dynamic Verification Engineer proficient in FPGA co-design, UVM verification, and award-winning privacy solutions.
National Yang Ming Chiao Tung University Taiwan
