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1. RISC-KC/basic_rv32s RISC-KC/basic_rv32s Public

   🎓 Instructional RISC-V processor design framework: single-cycle to 5-stage pipeline with FPGA verification and complete learning guidelines! A RISC-V CPU design guideline.

   Verilog 5

2. riscv/learn riscv/learn Public

   Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

   1k 112

3. RISC-KC/ima_make_rv64 RISC-KC/ima_make_rv64 Public

   I'ma make rv64 cpu.

   1