Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 info@chipsalliance.org

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 4.4k 637

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.5k 1.2k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.6k 250

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1.2k 353

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 892 232

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 747 181

Repositories

Showing 10 of 110 repositories
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 110 Apache-2.0 61 82 17 Updated Aug 29, 2025
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 125 Apache-2.0 66 174 75 Updated Aug 29, 2025
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,618 250 531 (16 issues need help) 26 Updated Aug 29, 2025
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 29 Apache-2.0 24 49 7 Updated Aug 29, 2025
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 407 Apache-2.0 76 46 (2 issues need help) 0 Updated Aug 29, 2025
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 285 Apache-2.0 39 18 24 Updated Aug 28, 2025
  • i3c-core Public
    chipsalliance/i3c-core’s past year of commit activity
    SystemVerilog 33 Apache-2.0 10 12 1 Updated Aug 29, 2025
  • sv-tests-results Public

    Output of the sv-tests runs.

    chipsalliance/sv-tests-results’s past year of commit activity
    HTML 7 6 0 0 Updated Aug 29, 2025
  • adams-bridge Public

    Post-Quantum Cryptography IP Core (Crystals-Dilithium)

    chipsalliance/adams-bridge’s past year of commit activity
    SystemVerilog 34 Apache-2.0 7 10 1 Updated Aug 28, 2025
  • Caliptra Public

    Caliptra IP and firmware for integrated Root of Trust block

    chipsalliance/Caliptra’s past year of commit activity
    321 Apache-2.0 49 57 3 Updated Aug 29, 2025
View all repositories