VHDL-Utils

A collection of reusable VHDL utilities, components, and testbenches to accelerate hardware design workflows. This repository provides tested, reliable building blocks for digital design projects with comprehensive simulation support.

The utilities are designed to work with VHDL-2008 simulators and include support for VUnit framework and OSVVM for enhanced testing capabilities.

Requirements

• VHDL Simulator: Any simulator that supports VHDL-2008
• IDE (Optional but recommended):
  • VSCode latest with VHDL language support:
    • TerosHDL by Teros Technology
    • VHDL-LS by Henrik Bohlin
• Python 3.11+ (Optional): For VUnit-based simulation automation

Initial Setup

Clone repository

• Open terminal
• Run git clone git@github.com:nselvara/VHDL-Utils.git
• Run cd VHDL-Utils
• Run code . to open VSCode in the current directory

Available Components

This repository includes the following VHDL utilities and components:

Core VHDL Utilities (utils_pkg.vhd)

• Unit conversion functions:
  • to_real() - Convert frequency_t or time values to real numbers (Hz or seconds)
  • to_time() - Convert frequency_t to time (period calculation)
  • to_frequency() - Convert time to frequency_t
  • to_clock_cycles() - Convert time duration to number of clock cycles at given frequency
• Bit calculation functions: to_bits() - Calculate minimum bits needed to represent a number
• Boolean conversion: ?? operator - Convert boolean to std_ulogic
• Vector operations: ** operator - Create UNRESOLVED_UNSIGNED vectors
• File operations: file_length_in_characters() - Get file size in characters
• Signal analysis: get_amount_of_state() - Count occurrences of specific states in vectors
• Trailing state counting: get_amount_of_trailing_state() - Count trailing bits of a given value in a vector
• Lowest/highest active bit: get_lowest_active_bit(), get_highest_active_bit() - Find the lowest/highest set bit in a vector
• One-hot/one-cold detection: is_one_hot(), is_one_cold() - Check if a vector is one-hot or one-cold encoded
• Relative equality: is_relatively_equal() - Compare two real numbers with tolerance

Testbench Utilities (tb_utils.vhd)

• Clock generation:
  • generate_clock() - Basic clock generation with frequency control
  • generate_clock() with reset - Clock generation with reset synchronization
  • generate_derived_clock() - Derived clock generation with division factors
  • generate_advanced_clock() - Clock with phase, duty cycle, and enable control
• Integer vector to string: to_string() - Convert integer vectors to string for debug output
• Reset patterns: Predefined weight distributions for realistic reset scenarios
• Random signal generation: 50/50 weight distributions for balanced testing

Simulation Support

• VUnit integration (run_all_testbenches_lib.py): Python library for automated testbench execution
• Xilinx library support: Automatic glbl module handling for Xilinx simulations
• Wave file automation (find_wave_file.do): ModelSim script for automatic wave file loading

Usage

To use these utilities in your VHDL projects:

1. Include the relevant package files in your project

2. Add the appropriate use statements in your VHDL files:

   library work;
   use work.utils_pkg.all;     -- For general utilities
   use work.tb_utils.all;      -- For testbench utilities

3. For VUnit-based testing, use the provided Python library to automate simulation runs