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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 21 public repositories matching this topic...

veryl

veryl-lang / veryl

Veryl: A Modern Hardware Description Language

rust rtl verilog systemverilog hdl

Updated Sep 5, 2025
Rust

yupferris / kaze

An HDL embedded in Rust.

rust hdl digital-logic-design

Updated Nov 15, 2023
Rust

pc2 / sus-compiler

A new Hardware Design Language that keeps you in the driver's seat

programming-language tree-sitter fpga hdl hardware-description-language fpga-programming

Updated Sep 5, 2025
Rust

chaseruskin / orbit

Package manager and build system for VHDL, Verilog, and SystemVerilog

package-manager asic fpga cross-platform hardware vhdl rtl verilog build-system command-line-tool systemverilog hdl

Updated Sep 4, 2025
Rust

pku-liang / Cement

The Next-gen Language & Compiler Powering Efficient Hardware Design

rust compiler hdl

Updated Jan 16, 2025
Rust

Jacajack / hdl

A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding

fpga verilog systemverilog hdl hardware-description

Updated Mar 3, 2025
Rust

Artentus / QuartzHDL

Hardware description language with Rust-like syntax

transpiler verilog systemverilog hdl

Updated Jan 17, 2025
Rust

jmorgadov / logix

Digital circuit simulation tools

simulation hdl digital-circuit-simulator

Updated Oct 8, 2024
Rust

tsheinen / nand2tetris-hdl-visualizer

Utility to visualize HDL files from Nand2Tetris as GraphViz DOT files

graphviz nand2tetris hdl visualize-hdl-files

Updated Oct 6, 2020
Rust

DvvCz / viva

Experimental cli to create HDL projects using Vivado, outside of their IDE.

rust cli package-manager hardware verilog vivado systemverilog hdl

Updated Oct 28, 2024
Rust

sigma-logic / gowiners

Gowin EDA thin oxidized wrapper

rust fpga hardware verilog hdl system-verilog hardware-design

Updated May 21, 2025
Rust

NoodlesOfWrath / ACL

Analog Computing Language

hdl

Updated Oct 14, 2024
Rust

tsheinen / nand2tetris-hdl-parser

parser nand2tetris hdl

Updated Aug 25, 2021
Rust

elias-2001-de / open-gal

Open-GAL is a hardware description language (HDL) designed for Generic Array Logic (GAL) chips.

rust hdl gal

Updated Aug 26, 2025
Rust

sux2mfgj / nslfmt

A nslfmt is a code fomatter written in rust for NSL which is one of the HDL and a succsesor of SFL.

rust hdl code-formatter nsl

Updated Dec 28, 2018
Rust

YSawc / embassyFc2

developing NES on FPGA project.

rust nes hdl embassy family-computer famicon veryl

Updated Jul 29, 2024
Rust

matth2k / safety-net

A reference-counted netlist library for EDA tool development

rust eda rtl verilog hdl netlist

Updated Sep 3, 2025
Rust

divtor / hdl-eval-rs

RustHDL & RHDL Evaluation + Board Support Package (BSP)

rust fpga bsp hdl ice40 icestick rusthdl rhdl

Updated Aug 26, 2025
Rust

Davoodeh / verilog2hspice

Do some simple conversions on Verilog files to make them compatible with HSpice

converter verilog hdl hspice

Updated Feb 13, 2023
Rust

jasonyu1996 / schemeview

asic fpga systemverilog hdl

Updated Apr 1, 2025
Rust

Followers: 488 followers
Website: github.com/topics/verilog
Wikipedia: Wikipedia