pipelined-processor

Here are 8 public repositories matching this topic...

yusronizza / riscv

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

open-source processor-architecture processor risc risc-v processor-design singlecycle-processor pipelined-processor

Updated Jan 7, 2025
Verilog

SaiManojGubbala / RISC-V

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A 32 Bit RISC-V Processor Implementation in Verilog

risc-v riscv32 verilog-project pipelined-risc pipelined-processor

Updated Apr 18, 2025
Verilog

EslamAsHhraf / Pipelined-Processor

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🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

python state-machine memory processor instrumentation verilog buffers computer-architecture registers program-counter control-unit pipline pipline-operators cufe-2024 execution-unit pipelined-processor

Updated Oct 16, 2023
Verilog

StackedArchitect / Fault-Tolerant-RISCV

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A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

fpga fault-tolerance riscv verilog computer-architecture error-detection-correction triple-modular-redundancy secded pipelined-processor

Updated Jun 26, 2025
Verilog

StackedArchitect / MIPS32Bit-Pipelined-CPU

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This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning about pipelined processor design and simulation.

cpu verilog vivado risc mips-architecture mips32 custom-processor pipelined-processor